Microelectronics Engineer

Microelectronics Engineer — Vertex Microchip Technologies

San Jose, CA | January 2024 – Present

• Designed and verified 3 analog-to-digital converter (ADC) blocks using Cadence Virtuoso, achieving a 15% reduction in power consumption and meeting all bandwidth targets.
• Led physical layout optimization for a mixed-signal microcontroller using Cadence Virtuoso, reducing die area by 12% and increasing packaging yield by 4% across 2 manufacturing runs.
• Automated parasitic extraction and post-layout SPICE simulations by authoring custom Python and TCL scripts, reducing design validation cycles by 25% for 5 engineering teams.
• Monitored post-silicon validation testing for 4 high-frequency RF transceiver prototypes using high-speed oscilloscopes, identifying 2 impedance mismatch sources before production.

Associate Microelectronics Engineer — Lumina Semiconductor Systems

Santa Clara, CA | August 2021 – December 2023

• Performed SPICE circuit simulations and thermal analysis on 12 power management integrated circuits (PMICs), improving thermal dissipation efficiency by 18%.
• Collaborated with fabrication engineers to debug wafer mask defects, utilizing scanning electron microscopy (SEM) to reduce defect-related scrap by 22% over 6 months.
• Programmed FPGA-based prototyping boards to test digital logic designs, reducing hardware-in-the-loop simulation debug times by 30% for next-generation microprocessors.
• Streamlined design documentation processes for 8 integrated circuits using Confluence, ensuring 100% compliance with industry safety standards and layout guidelines.

Analog & digital IC design, Mixed-signal design, Cadence Virtuoso, Synopsys Design Compiler, SPICE simulation, Physical layout design, Parasitic extraction, FPGA prototyping, Verilog, VHDL, Python, TCL, MATLAB, Scanning Electron Microscopy (SEM), Silicon wafer fabrication, Semiconductor physics

Low-Power 12-bit SAR ADC Design

Role: Lead IC Design Engineer

Tools: Cadence Virtuoso, HSpice, MATLAB

Designed and simulated a 12-bit SAR ADC in 65nm CMOS, reducing power consumption by 22% compared to previous architectures.

Automated Parasitic Extraction Pipeline

Role: Microelectronics Engineer

Tools: Python, TCL, Calibre, Synopsys

Created automation scripts for post-layout parasitic extraction, reducing design validation iteration time by 35.

• Cadence Certified Virtuoso Custom IC Design Professional (2022)
• Synopsys Custom Compiler Certified Professional (2023)
• IPC CID+ Certified Interconnect Designer (2024)

• Languages: English (Native), Vietnamese (Conversational)
• Volunteer Work: Engineering mentor for local FIRST Robotics competition teams (2022-present)
• Availability: 3 weeks notice