Hardware Engineer

Hardware Engineer — Helix Circuits

San Jose, CA | June 2024 – Present

• Designed and routed 6-layer high-speed digital circuit boards using Altium Designer, reducing signal-to-noise ratio distortion by 18% and board footprint by 15% through precision layout routing.
• Formulated power distribution network simulations in LTspice, resolving a critical power rail ripple issue and recovering 14% efficiency on the core microcontroller voltage supply line.
• Operated digital oscilloscopes, spectrum analyzers, and thermal cameras to identify and resolve EMI emissions, ensuring compliance with FCC class B certification on 4 consumer products.
• Collaborated with firmware developers to program microcontrollers in C/C++, improving peripheral sensor polling rates by 22% and reducing system boot-up time from 3.2 seconds to 1.8 seconds.

Hardware Designer — Vortex Embedded Systems

Seattle, WA | August 2021 – May 2024

• Created schematic designs and multi-layer layouts for 12 prototype microcontroller modules using KiCad, reducing hardware design error rates by 32% across subsequent production runs.
• Constructed and soldered 45 custom testing boards, maintaining a 98% component yield rate and cutting manual circuit debugging times by 26% through the creation of new hardware check templates.
• Authored Python testing scripts to automate data collection from climate chambers and voltage sweeps, decreasing manual verification testing cycles by 35% for design verification testing.
• Evaluated 28 vendor component datasheets for cost optimization, proposing alternative low-dropout regulators that reduced unit production expenses by 14% while retaining reliability.

PCB Layout, Schematic Capture, High-Speed Digital Design, Power Integrity, LTspice, Altium Designer, KiCad, Microcontrollers, C/C++, Python, Oscilloscopes, Spectrum Analyzers, Signal Integrity, ESD Protection, Soldering, Lab Testing, EMI/EMC Compliance

High-Speed Microprocessor Carrier Board

Role: Lead Hardware Engineer

Tools: Altium Designer, LTspice, HyperLynx, DDR4

Designed a 6-layer carrier board supporting DDR4 memory interfaces, ensuring impedance matching within 2% and eliminating signal reflections completely.

Low-Power Wearable Sensor Node

Role: Hardware Designer

Tools: KiCad, Nordic nRF52, BLE, C

Engineered a low-power power management integrated circuit layout, reducing sleep current draw by 35% and extending device battery life by 6 months.

• IPC-CID (Certified Interconnect Designer) (2023)
• Altium Certified Professional (2022)

• Languages: English (Native), Spanish (Conversational)
• Patents: Co-inventor on US Patent for low-noise sensor signal conditioning circuit (2025)
• Volunteer Work: STEM mentor for local high school robotics teams (2022 – present)
• Availability: 2 weeks notice